The digital revolution has profoundly reshaped how we communicate, work, and travel by redefining our relationship with the world. Digital electronic devices have created an expansive network of portable, interactive, and accessible communication tools. However, the true potential of digital technology is only realized when it can accurately replicate the original analog signals using binary "1" and "0." This requires a seamless translation between digital and analog domains, ensuring that the information remains faithful to its source.
Advancements in the digital era have followed Moore’s Law, where the number of transistors on a chip doubles approximately every 18 months. In contrast, analog technology operates under Murphy’s Law—anything that can go wrong will. While analog development progresses at a more steady pace, it relies less on process improvements and more on innovations in circuit modeling and physical transistor design. These advancements lead to better performance, lower power consumption, and greater integration across multiple dimensions.
The trend toward integration varies depending on production maturity and system requirements. In many cases, achieving system approval and unit yield doesn’t always confirm that iterative development was the right approach. In applications like base stations, instrumentation, and military systems, strict performance demands often necessitate discrete solutions. Meanwhile, in user-accepted technologies such as cellular and Wi-Fi networks, competitive pressures push for continuous cost reductions. As technology deployment becomes more expensive—due to masking processes, test tools, and engineering costs—companies must ensure returns to support growing R&D investments. Competitive forces also drive heavy early-stage investment in standard lifecycles. If a company's chipset isn't ready when the market takes off, the consequences can be severe.
To stay ahead, companies must invest heavily upfront, and this investment is rising. At the same time, customers demand higher performance from their suppliers. The challenge now is to achieve acceptable returns from the complex R&D required for modern communication systems. For example, the development cost of a 90nm SoC can easily exceed $10 million to $20 million. A new design’s success depends on the value of its IP and the choice of partners to meet evolving user needs. Fewer companies can address all aspects of system development, but the core requirements remain: managing performance costs, reducing time to market, and maximizing return on capital.
For emerging communication applications like WiMAX, first-generation systems are typically built using multi-chip ICs. The MAC and modem sections may use FPGAs and off-the-shelf DSPs, while the RF section often relies on discrete components like LNAs, mixers, and frequency synthesizers. As production scales, digital logic is often integrated into ASICs, and in some cases, ADC/DAC functions are also included for highly integrated RF solutions. In compact devices like cell phones or USB dongles, both analog and digital blocks must be integrated—either in a multi-chip module or on a single chip. There are various ways to reduce chip size and cost, and the current trend is to increase production volume, which can lead to higher chip area and cost. In some cases, cost is the priority, and RF performance may be compromised (as seen in some consumer WLAN products), though users might not even notice. In others, chip size is critical, driving the need for functional integration.
Success in this space comes from a variety of strategies. Companies have achieved it through different integration approaches and cost-cutting methods. Clearly, the choice of development solution must minimize eBOM, package size, and time to market. Smart system partitioning plays a key role in achieving these goals.
Traditional Division Method: Time-to-Market Risk
Integrating mixed-signal circuits into a digital ASIC brings numerous challenges, including time-to-market delays and increased risk. Even if the analog core is verified separately, its performance is influenced by the integration environment. Power supply routing, parasitic capacitance, and process variations—often negligible in pure digital chips—now become significant factors.
From an FPGA-verified digital design to tape-out, the process typically takes 2 to 6 months, depending on complexity and tools. However, integrating a mixed-signal design to tape-out can take three times longer, assuming the analog core is available and the process is suitable. Analog circuits operating at microvolt levels are highly sensitive to noise from digital switches, requiring careful design, multiple checks, and additional engineering time.
While the issue is manageable, it demands custom mask layout design and specialized engineering resources. Sometimes, developing new core capabilities exceeds the team’s existing skills.
The evaluation board’s design and routing also significantly affect the performance of the mixed-signal section. The analog I/O on the reference design is vulnerable to external noise, so the power distribution for the mixed portion must be well-isolated. Removing analog I/O helps reduce noise coupling and resolve interface issues between analog cores from different vendors, such as RF chips and ADCs. Some ADCs recommend using a discrete 5V op-amp buffer to meet performance specifications. For modems using smaller linewidth processes (like 130nm or 90nm), signal swings and common-mode levels must be carefully matched when integrating RF chips from different manufacturers. These considerations require valuable engineering time and resources.
To capture market share, being second often means drastically cutting prices. Choosing a purely digital or FPGA-based design flow can save 6 to 12 months in time-to-volume production.
Getting the right silicon is just the start. Putting a mixed-signal IC into production presents its own set of challenges. Mixed-signal circuits are sensitive to process variations like threshold voltage, leakage, and material resistance. As mixed-signal performance declines, overall system performance follows. For mass-produced products, having multiple manufacturing sites is essential for timely delivery and cost efficiency. While choosing a digital manufacturer is straightforward, transferring mixed-signal production to another vendor is time-consuming and may require extensive redesign and optimization. Integrating with different manufacturing processes can be difficult, even if they are used successfully elsewhere.
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