The baseband fiber optic solution involves relocating the intermediate frequency section of a digital microwave relay system from the indoor unit to the outdoor unit. By using optical fiber as the transmission medium and sending baseband digital signals, the system can achieve transmission distances of several kilometers or more. This approach eliminates the need for traditional feeder cables between the indoor and outdoor units, significantly reducing signal loss and the power requirements for the power amplifier. Most importantly, it allows greater flexibility in antenna positioning, as it is no longer constrained by the location of the indoor unit. This enables optimal placement based on environmental conditions, making device installation easier and more efficient. This paper presents an overview of the 88E1111 chip and proposes a design scheme for the baseband fiber optic remote connection of a digital microwave relay system, solving the complexity and implementation challenges associated with such interfaces.
1. Introduction to 88E1111
1.1 Features of 88E1111
The 88E1111 is a high-performance Gigabit Ethernet physical layer (PHY) chip developed by Marvell. It supports the entire IEEE 802.3 protocol suite and includes a built-in 1.25 Gbps serial deserializer for use in gigabit optical transmission applications. The chip supports multiple MAC layer interfaces such as GMII, TBI, RGMII, and RTBI, and provides adaptive detection for 10/100/1000BaseT. It uses 0.13 μm CMOS technology, operates on low voltages (2.5 V and 1.2 V), consumes up to 0.75 W, and supports automatic power reduction.
1.2 Interface of 88E1111
1) The GMII interface connects the 88E1111 to the MAC layer. Table 1 shows the data interface connections.
2) The management interface consists of MDC and MDIO signals. MDC provides the clock signal at up to 8.3 MHz, while MDIO transmits data synchronized with MDC. A "0 1" pattern in the data stream indicates the start of an operation, followed by the opcode (read or write), physical address, register address, and data. The CPU controls the chip by accessing these registers.
3) The LED/Configuration interface includes LED_Link10, LED_Link100, LED_Link1000, LED_TX, LED_RX, LED_Duplex, VDDO, and VSS. The configuration interface uses Config[6:0] to set the operating mode. Table 2 shows the typical mapping for 1000BaseX and full-duplex mode.
4) The high-speed serial interface uses three pairs of differential signals. The interface level is CML, with S_IN± for incoming data, S_OUT± for outgoing data, and SD± for optical power monitoring.
1.3 88E1111 Registers
The 88E1111 has 32 16-bit control registers with addresses ranging from 00H to 1FH. These registers are used for chip reset, rate setting, and duplex mode configuration. Their functions are detailed in Table 3.
2. Program Design
Based on the functionality of the 88E1111 and the requirements of the baseband fiber optic system, this paper proposes an interface design for the digital microwave relay system. The block diagram of the interface is shown in Figure 1, consisting of an indoor unit and an outdoor unit. In the transmit direction, the service code stream from the indoor unit is processed by the FPGA complex resolver, packaged into an IEEE 802.3 compliant frame, and sent to the 88E1111 via the GMII interface. The chip then converts the data into a serial format and sends it through the high-speed serial interface to the 1.25 G optical transceiver, which converts the electrical signal to an optical one for transmission. At the outdoor unit, the optical signal is converted back to electrical and processed by the 88E1111 before being sent to the FPGA modem for demodulation and RF transmission. The return path follows the reverse flow.
3. Hardware Design
Figure 2 shows the circuit schematic of the 1.25 G optical transceiver SSFF315l. Its RD± and TD± pins are connected to the S_IN± and S_OUT± signals of the 88E1111. Figure 3 shows the 88E1111 circuit schematic. Key connections include the GMII interface (see Table 1 for FPGA connections), the management interface (MDIO and MDC connected to the microprocessor), the configuration interface mapped according to Table 2, the XTAL1 pin receiving a 125 MHz clock, RSET connected to ground through a 5 kΩ resistor, and SEL_FREQ set to low for 125 MHz input.
The 88E1111 fully complies with the IEEE 802.3 protocol. TX_CLK is the transmit clock, and TX_EN enables data transmission on its rising edge. RX_CLK and RX_DV work similarly for reception.
4. Issues to Consider in the Design
4.1 Electrical Interface Matching
The 88E1111 uses a CML interface, while the optical transceiver uses LVPECL. An AC-coupled matching circuit should be added between them. On the transmitter side, biasing resistors (R9 and R10) of 142–200 Ω are placed between the LVPECL outputs and ground. On the receiver side, a 100 Ω resistor is connected between the LVPECL inputs.
4.2 GMII Interface Design
The GMII interface operates at 125 Mb/s. To avoid phase errors due to PCB propagation delays, TXD[7:0], CTX_CLK, and TX_EN form one group, and RXD[7:0], RX_CLK, and RX_DV form another. Both groups must have equal trace lengths.
4.3 PCB Layout Design
The baseband fiber optic board includes LVTTL, LVPECL, and CML signals. To reduce interference, differential pairs should be kept short and evenly spaced to maintain consistent differential impedance.
5. Conclusion
The baseband fiber optic remote interface designed around the 88E1111 achieves a data transmission rate of 800 Mb/s in gigabit and full-duplex mode, with a transmission distance of up to 20 km over single-mode fiber. This meets all design requirements for digital microwave relay systems. The solution has been widely implemented in commercial products, offering a simple, stable, and cost-effective alternative to traditional designs. Compared to conventional approaches, two key innovations stand out: first, the use of IEEE 802.3-compliant data frames ensures standardization and reliability; second, the adoption of optical fiber eliminates the need for feeders between indoor and outdoor units, reducing both cost and installation complexity.
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