**Introduction**
Author: Alex He (Ho Ye), Senior Applications Engineer at Xilinx.
UIO stands for Userspace I/O, a small but powerful component in the Linux kernel world. It is mainly used for custom devices and their corresponding drivers. The UIO kernel driver exposes device memory and interrupts to user space, allowing user-space applications to interact directly with hardware. This design offers high flexibility and customization, making it ideal for specialized use cases.
So how does this relate to FPGAs? Well, FPGAs are highly programmable, and when paired with UIO, they can be controlled directly from user space, enabling efficient hardware acceleration and real-time control.
This lab project demonstrates how to implement multiple UIOs on the Zynq UltraScale+ MPSoC ZCU102 evaluation board using Xilinx tools. We’ll cover hardware design, Linux BSP development, and test applications. The ZCU102 features a quad-core ARM Cortex-A53, dual-core Cortex-R5, and a Mali-400 GPU (PS), along with an FPGA (PL) that can be used for custom logic and acceleration. The PS handles control, while the PL accelerates specific tasks via AXI interfaces.
**Experimental Report**
Experimenter: Me
**Materials Used:**
- ZCU102 Evaluation Board
- Vivado Design Suite
- Petalinux Tools
- DIP Switches
- Terminal Emulator
**Hardware Design**
We created a Vivado project for the ZCU102. Using IP Integrator, we connected the Processing System (PS) and added 5 UIO inputs on the Programmable Logic (PL) side. One of these was a GPIO module with interrupt output and memory mapping, while the other four were connected to DIP switches through a Concat IP block, which then linked to the PS’s `ps_pl_irq` pin. For more details, refer to [1] UG1182 and [2] UG1085.
We added PIN constraints to ensure proper signal routing. The design was completed quickly using Vivado’s graphical interface and rich IP library.
**Software Design**
We used Xilinx Petalinux to build the Linux BSP. Based on Yocto, Petalinux simplifies the process of integrating hardware, building the kernel, and packaging the system. We enabled the `uio_pdrv_genirq` driver, which allows user-space applications to handle interrupts.
The steps included creating a project, configuring the hardware description, enabling the UIO driver, modifying the device tree, and generating the boot image.
In the device tree, we manually adjusted the GPIO UIO node and added entries for the DIP switches. Each UIO device must have a compatible string set to “generic-uio†and the correct interrupt number assigned.
**Testing**
After booting the system and loading the driver, we checked `/proc/interrupts` to verify that the UIO interrupts were properly registered. However, we noticed two missing interrupts due to hardware limitations in triggering modes.
For testing, we toggled the DIP switches and observed the interrupts. A simple user-space application was written to read from `/dev/uioX`, and by writing to the device, we could enable or disable interrupts.
For the GPIO UIO, we used `mmap` to access the register space and tested interrupt generation by setting up the GPIO interrupt enable registers.
**Conclusion**
This experiment showcases how UIO can be effectively used with Xilinx MPSoCs to create flexible and customizable embedded systems. The combination of hardware and software tools provided by Xilinx makes development efficient and straightforward. Though the example is simple, it highlights the power of All Programmable platforms and the potential for FPGA-based acceleration.
All code, hardware files, and test scripts are available on Git: https://gitenterprise.xilinx.com/AlexHe/UIO_Linux_Demo.
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