In this article, I will introduce an interesting clock chip feedback mechanism. It might occur unexpectedly or as part of a test or recovery process, but it's generally something to be avoided, as explained below. Understanding the Ouroboros clock configuration can also help explain some unusual behaviors in complex timing systems.
Before diving into the "Ouroboros" clock, let's first review some basic clock switching terminology and standard input clock configurations. Click on "Read the original" to watch the full text!
**Some basic clock switching terms**
Clock chips typically support switching between input clocks based on certain conditions, such as LOS (Loss of Signal) or OOF (Out of Frequency). Here are the most commonly used terms:
**Free mode**
In free mode, the output clock is based on an internal crystal or resonator rather than an external reference. The frequency stability, drift, and jitter of the output clock depend solely on the internal oscillator, independent of any input clock.
**Hold mode**
When the input clock is lost and no valid backup is available, the device enters hold mode. In this mode, the output clock is based on historical frequency data from the last valid input clock. The accuracy of the output depends on how long and how accurately that data was collected.
**Lock mode**
In lock mode, the output clock is locked to the selected input clock, which is the normal operational state.
**Standard input clock switching configuration**
Consider the illustration of two jitter attenuator clock ICs cascaded as shown in the figure below. This setup may be used for additional jitter reduction or for optimizing frequency distribution. For simplicity, these devices are represented as a Si5345 block diagram.
In the figure, IN0 and IN3 provide two input clocks to Device #1. Typically, one clock acts as the "master" while the other serves as the "auxiliary." The master could be recovered from network data, while the auxiliary relies on a local oscillator. If the primary clock fails or is disqualified by LOS or OOF, the clock chip switches to the secondary clock, usually to keep downstream equipment running. When the primary clock becomes valid again, the chip may switch back, depending on the configuration.
The key point here is that as long as at least one of these clocks is present, a valid lock mode clock is generated at OUT0, providing an input to downstream Device #2. However, if both input clocks for Device #1 are lost, the device may enter hold or even free mode, still producing a temporary stable output.
**Clock configuration**
In standard applications, the downstream clock is not fed back to the upstream input. Instead, it is typically a scaled or jitter-attenuated version of an upstream clock. But what happens if we try the configuration shown in Figure 2?
In this case, one of the outputs from downstream Device #2 is fed back to upstream Device #1. This could serve as a temporary backup clock.
Now, as shown in Figure 3, what happens when the main clock IN0 is lost? The auxiliary clock IN3 to Device #1 depends on the output of Device #2. Note that this is just a locked version of Device #1's output. While such a configuration isn't common, it occasionally appears in applications involving two devices.
This is known as the **Ouroboros** clock configuration. The name comes from the ancient symbol of a snake eating its own tail, representing a loop or cycle. According to Wikipedia, the term originates from the Greek words "ourá" and "bóros," meaning "to swallow." The Ouroboros symbol represents an eternal cycle, making it a fitting name for this configuration.
**Gedanken experiment**
Let’s consider a simple thought experiment with a basic PLL. Assume it has been placed in the Ouroboros configuration, as shown in Figure 5.
If everything were ideal and there were no PFD (Phase Detector) error, the system would at least appear stable. However, even without loop noise, there is likely a fixed phase offset between the signals presented to the PFD (+) and PFD (-). In normal PLL operation, the VCO adjusts to align the output clock with the input. In the Ouroboros configuration, however, the VCO cannot reduce the phase error.
Assume the output clock is measured in phase under PFD (+) versus PFD (-). The loop will then attempt to track by tuning the VCO to a higher frequency. But the phase difference remains, causing the loop to continue trying to correct it until the VCO reaches its maximum frequency.
**Experiment**
So, what actually happens in real situations? Consider a project plan with the following settings:
- Nominal bandwidth: 100.000 Hz
- Quick lock enable: On
- Exit from Holdover: Enabled
- OOF thresholds for IN0 and IN1: 100 ppm (assertion), 98 ppm (deassertion)
Using two Si5345 evaluation boards, where instead of IN1, IN3 is used as the secondary clock. Apply a signal generator to Device #1 IN0 and run both boards until HOLD_HIST_VALID is true. What happens when the 100 MHz input clock on IN0 is removed?
Initially, only LOS [0] is reported by Device #1. Everything else seems fine. However, the output clock frequency from Device #2 starts to increase. Eventually, Device #2's output exceeds the OOF threshold of Device #1. The result is:
- Device #1 enters hold mode
- Device #2 remains in lock mode
Note that each device can become unstable in the opposite state. Our experience shows that most of the time, there are preferred states, but sometimes you see alternating behavior, almost like a chaotic system.
In this case, the Ouroboros configuration doesn’t really offer any benefit, except possibly in rare cases. However, the output frequency triggers an OOF [1] on Device #1, and Device #2 still depends on Device #1's HO clock throughout. This is a potential problem in this unrealistic configuration.
**Ouroboros oscillation**
This configuration can also create a positive feedback system that leads to oscillations and strange behavior. This can happen if one of the devices can exit hold mode. For example, if the OOF thresholds are tightened as follows:
- OOF thresholds for IN0 and IN1: 0 ppm (assertion), 9,375 ppm (deassertion)
The two devices may interact and never stabilize. Below is the frequency plot of Device #2's output clock. You can see that the output frequency slowly oscillates every 8–9 seconds.
There are three status states on Device #1 due to the varying output frequency of Device #2:
1. Device #1 is in hold (HO) mode
2. Device #1 exits HO mode
3. Device #1 re-enters HO mode
During this time, Device #2 does not issue an alarm. This state can persist indefinitely. I started this experiment on Friday afternoon and it was still running on Monday morning. The devices can even swap roles depending on their HO state. This kind of constant entering and exiting of HO mode is worse for equipment than simply staying in HO.
**Conclusion**
In summary, the Ouroboros clock configuration either serves no useful purpose beyond delaying into hold mode or can trigger oscillations that cause repeated instability in the output clock. Generally, the downstream clock should remain downstream and not feed back into the upstream system.
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