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The μPLAT series based on an ARM CPU and integrated with peripheral functions such as real-time operating system timers is a basic system-level LSI development platform. The high-speed and low-power μPLAT-92 platform was developed for W-CDMA, PDA and other portable devices such as Internet devices. μPLAT-92 is a platform for hardware development and integration environments characterized by hard IP: μPLAT-92 core includes an ARM920T The CPU and the minimum peripheral I/O devices required to run the operating system; power management IP and prototyping boards are also included. This not only improves the speed and power consumption of system-level LSIs, but also shortens the development time of large-scale system-level LSIs with increasing scale, and enables users to focus on their own custom application development and quality improvement.
μPLAT-92 architecture
In exploring the combination of reduced size and weight with high-speed performance, many system LSI designers are working to reduce the scale of development cycles and maintain or improve product quality. But they also face the following obstacles that seem insurmountable:
1. As the CPU peripheral circuit runs faster, the critical path occurs and the timing design cannot be constrained;
2. Power consumption increases with increasing speed;
3. The peripheral IO and external interface circuitry must be designed to accommodate high speed, low power operation and real-time operating system instruction execution (timers and interrupts, etc.).
μPLAT is a solution to solve the above problems.
(1) Hardware structure
The hardware composition of μPLAT-92 is shown in Figure 1.
μPLAT-92 includes μPLAT-92 core and peripheral IP, namely clock generator module (CGB), μPlat power control (PPWC), power down coverage (PDW) and so on. The μPLAT-92 core includes an ARM920T CPU, an external memory controller (MemCon), an interrupt controller (IntCon), an operating system timer (timer), a serial interface (SIO), and a system controller that includes power management ( SysCon) and a test interface (TIC). The AMBA bus recommended by ARM is used as a chip bus. The AMBA bus includes a high speed system bus, an advanced high performance bus (AHB), a medium/low speed system bus, and an advanced peripheral bus (APB). AHB is used to connect to the μPLAT-92 core.
The μPLAT-92 core provides a 0.16μm CMOS processing hardware IP.
(2) Power management
Power management functions are implemented by power management IP (CGB, PPWC, and PDW) and combined with the μPLAT-92 core. The power management IP is listed in Table 1.
The μPLAT-92 has power management functions based on clock adjustment, single clock pause, all clock pauses, and power-off operations, allowing dynamic switching based on fine division of the operating clock frequency.
Software control for power management is achieved by providing operational power management functions (sampling) to allow users to integrate complex power management controls.
Figure 2 is a block diagram of the power management architecture. If the circuit is built with a transistor with a standard threshold voltage (MVt transistor), high speed clock operation is possible, but the current (leakage current) at the time of clock stall will be greater than the current of the high threshold voltage transistor (HVt). In portable devices and similar applications, power consumption is lower in standby mode, but high-speed operation requires full-load operation, so reducing leakage current is important.
In μPLAT-92, the above problem can be solved by turning off the power of the MVt transistor module during standby to provide an LSI having an extremely low standby leakage current and a high clock speed in peak use.
Development of μPLAT-92
In the development of μPLAT-92, the following EDA tools and techniques were used in all design phases to improve design quality and shorten design time.
The front-end design phase uses RTL checkers and code coverage tools to improve quality. In addition, in order to achieve general availability, certain conditions must be assumed, so a Specman Elite for random analysis is used. And to shorten the design cycle, a comprehensive tool called Physical Compiler was used before the back-end design, which has excellent post-layout timing prediction capabilities to reduce backend rejection. In its final phase, a system-level constrained (SLC) process (using timing constraints to layout from the front end) was used to reduce layout rejection due to improper timing and thus achieve early timing compression.
Simulations were introduced during the early development phase to improve hardware stability by running checks and competitive testing of all OS functions (general and power management). Figure 3 shows a setup for this type of simulation: an Aptix System Explorer MP3C is used as an emulator, which downloads the netlist from the workstation to the FPGA via Ethernet and downloads the test for analysis from the PC via parallel JTAG. Model (TP). A serial port receiver for testing the internal SIO of the μPLAT-92 is connected between the PC and the emulator. In this way, accurate simulation real-time analysis can be performed prior to wafer fabrication, helping to improve the quality of the μPLAT-92 core and shorten the development cycle.
Hardware development environment
(1) μPLAT-92 prototype board
Figure 4 shows the block diagram of the μPLAT-92 prototype board. The prototype includes: an evaluation chip including μPLAT-92 core, power management IP and ETM9 (embedded trace macro); an FPGA containing AHB-APB bridges connected to AMBA AHB, GPIO, UART and DMAC (standard ); a user FPGA (optional); and APB, AHB, and EXMEM connectors that form the user extension interface.
Use a JTAG interface and a real-time trace port for debugging. A PC is connected to the JTAG interface via Oki-ADI (ARM Debug Interface Board) and software and hardware debugging is performed by running ARM's Software Development Kit (SDT) on the PC.
With this prototype board, we can deploy the hardware circuits integrated in the system-level LSI on an optional FPGA, or on an FPGA on the AHB/APB/EXMEM expansion board, and perform its function before manufacturing the system LSI. And analysis of work characteristics.
(2) Test basis
Figure 5 shows the system-level LSI simulation environment test benchmark developed by us. The simulation environment can simulate the timing of the μPLAT-92 kernel model and system LSI model with peripheral logic.
The file generated by the ARM SDT after compiling the test model created in C language and assembly language and the CONF file for specifying the clock frequency setting and the memory attribute are input to the test reference, which runs on the same clock in μPLAT-92. The reference clock generated by the generator circuit. This setting allows for timing simulations related to the μPLAT-92 model, the user circuit model, and the IP model.
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